1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a metal-oxide-semiconductor field-effect transistor with improved protection against electrostatic discharge.
2. Description of the Related Art
The shrinking dimensions of complementary metal-oxide-semiconductor (CMOS) integrated circuits require special designs for transistors that conduct large amounts of current. Such transistors are found in particular in CMOS input and output circuits, where they are needed to drive heavy loads and to provide protection from electrostatic discharge (ESD).
One known high-current transistor design is the finger design illustrated in FIG. 1, which places multiple gate electrodes 1 between an alternating series of source 3 and drain 5 diffusions. If the transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, for example, the source and drain diffusions 3, 5 are n-type diffusions disposed in a p-type well or substrate 7, and the transistor is surrounded by a p+-type diffusion 9 through which a fixed potential is supplied to the well or substrate 7. Since the p+-type diffusion 9 helps prevent CMOS latch-up, it is also known as a guard ring. For an n-channel transistor, the source and guard ring diffusions 3, 9 are normally coupled to ground. The finger design provides ample total channel width to drive a large load, or to shunt ESD current safely from the drain diffusions 5 to the source diffusions 3.
As shown in FIG. 2, however, parasitic diodes 10 are formed between the ends of the drain diffusions 5 and the guard ring diffusion 9. If these diffusions 5, 9 are too close together, the parasitic diodes 10 may break down under ESD stress, leading to thermal damage as discharge current surges through the relatively small total diode width. To avoid such damage, enough space to prevent breakdown must be provided between the drain diffusions 5 and guard ring diffusion 9, but this increases the area of the transistor.
U.S. Pat. No. 5,714,784, issued to Ker et al., discloses an alternative design, shown in FIG. 3, in which a guard ring diffusion 9, source diffusion 11, and gate electrode 13 form concentric square loops converging on a central square drain diffusion 15. By separating the drain and guard ring diffusions, this design eliminates the parasitic diode shown in FIG. 2, enabling the transistor dimensions to be reduced without loss of ESD robustness.
The transistor in FIG. 3 is vulnerable to damage, however, at the overlapping corners 16 of the gate electrode 13 and drain diffusion 15. This problem is thought to result from electric field concentration combined with poor gate oxide quality at the corners 16. Although the failure mechanism is not understood in detail, it is known that in general the gate-drain breakdown voltage of a field-effect transistor decreases as the number of corners in its active region increases. The result of an oxide breakdown under ESD stress is often fatal to the device: the ESD current burns a hole through the oxide film.